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ON Semiconductort
SWITCHMODEt
NPN Bipolar Power Transistor For Switching Power Supply Applications
The MJE13007 is designed for high-voltage, high-speed power switching inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V switchmode applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits. * VCEO(sus) 400 V * Reverse Bias SOA with Inductive Loads @ TC = 100C * 700 V Blocking Capability * SOA and Switching Applications Information * Standard TO-220
MAXIMUM RATINGS
Rating Collector-Emitter Sustaining Voltage Collector-Emitter Breakdown Voltage Emitter-Base Voltage Collector Current -- Continuous Collector Current -- Peak (1) Base Current -- Continuous Base Current -- Peak (1) Emitter Current -- Continuous Emitter Current -- Peak (1) Total Device Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Symbol VCEO VCES VEBO IC ICM IB IBM IE IEM PD TJ, Tstg MJE13007 400 700 9.0 8.0 16 4.0 8.0 12 24 80 0.64 - 65 to 150 Unit Vdc Vdc Vdc Adc Adc Adc Watts W/C C
MJE13007
POWER TRANSISTOR 8.0 AMPERES 400 VOLTS 80 WATTS
THERMAL CHARACTERISTICS
Thermal Resistance -- Junction to Case -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes: 1/8 from Case for 5 Seconds RJC RJA TL 1.56 62.5 260 C/W
CASE 221A-09 TO-220AB MJE13007
C
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle 10%. *Measurement made with thermocouple contacting the bottom insulated mounting surface of the *package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied *at a mounting torque of 6 to 8*lbs.
(c) Semiconductor Components Industries, LLC, 2001
1
May, 2001 - Rev. 3
Publication Order Number: MJE13007/D
MJE13007
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic *OFF CHARACTERISTICS Collector-Emitter Sustaining Voltage (IC = 10 mA, IB = 0) Collector Cutoff Current (VCES = 700 Vdc) (VCES = 700 Vdc, TC = 125C) Emitter Cutoff Current (VEB = 9.0 Vdc, IC = 0) SECOND BREAKDOWN Second Breakdown Collector Current with Base Forward Biased Clamped Inductive SOA with Base Reverse Biased *ON CHARACTERISTICS DC Current Gain (IC = 2.0 Adc, VCE = 5.0 Vdc) (IC = 5.0 Adc, VCE = 5.0 Vdc) Collector-Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 8.0 Adc, IB = 2.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100C) Base-Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100C) DYNAMIC CHARACTERISTICS Current-Gain -- Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, f = 1.0 MHz) Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz) SWITCHING CHARACTERISTICS Resistive Load (Table 1) Delay Time Rise Time Storage Time Fall Time Inductive Load, Clamped (Table 1) Voltage Storage Time Crossover Time Fall Time * Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. VCC = 15 Vdc, IC = 5.0 A Vclamp = 300 Vdc IB(on) = 1.0 A, IB(off) = 2.5 A LC = 200 H TC = 25C TC = 100C TC = 25C TC = 100C TC = 25C TC = 100C tsv tc tfi -- -- -- -- -- -- 1.2 1.6 0.15 0.21 0.04 0.10 2.0 3.0 0.30 0.50 0.12 0.20 s s s (VCC = 125 Vdc, IC = 5.0 A, IB1 = IB2 = 1.0 A, tp = 25 s 10A s, Duty Cycle 1.0%) td tr ts tf -- -- -- -- 0.025 0.5 1.8 0.23 0.1 1.5 3.0 0.7 s fT Cob 4.0 -- 14 80 -- -- MHz pF hFE 8.0 5.0 VCE(sat) -- -- -- -- VBE(sat) -- -- -- -- -- -- 1.2 1.6 1.5 -- -- -- -- 1.0 2.0 3.0 3.0 Vdc -- -- 40 30 Vdc -- IS/b -- See Figure 6 See Figure 7 VCEO(sus) ICES -- -- IEBO -- -- -- -- 0.1 1.0 100 Adc 400 -- -- Vdc mAdc Symbol Min Typ Max Unit
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VCE(sat), COLLECTOR-EMITTER SATURATION VOLTAGE (VOLTS) 1.4 VBE(sat), BASE-EMITTER SATURATION VOLTAGE (VOLTS) IC/IB = 5 1.2 1 0.8 0.6 TC = -40C 25C 100C 10 5 2 1 0.5 TC = -40C 25C 100C 0.05 0.1 0.2 0.5 1 2 5 10 IC/IB = 5
0.2 0.1
0.05
0.4 0.01 0.02
0.05
0.1
0.2
0.5
1
2
5
10
0.02 0.01 0.01 0.02
IC, COLLECTOR CURRENT (AMPS)
IC, COLLECTOR CURRENT (AMPS)
Figure 1. Base-Emitter Saturation Voltage
Figure 2. Collector-Emitter Saturation Voltage
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
3 2.5 2 1.5 1 0.5 0 0.01 0.02 IC = 1 A IC = 5 A IC = 3 A IC = 8 A TJ = 25C
0.05
0.1
0.2
0.5
1
2
3
5
10
IB, BASE CURRENT (AMPS)
Figure 3. Collector Saturation Region
100
10000 TJ = 100C Cib C, CAPACITANCE (pF) 1000 TJ = 25C
hFE , DC CURRENT GAIN
25C 10 40C VCE = 5 V
Cob 100
1 0.01
0.1
1
10
10 0.1
1
10
100
1000
IC, COLLECTOR CURRENT (AMPS)
VR, REVERSE VOLTAGE (VOLTS)
Figure 4. DC Current Gain
Figure 5. Capacitance
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100 50 IC, COLLECTOR CURRENT (AMPS) 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 TC = 25C DC 5 ms
BONDING WIRE LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT CURVES APPLY BELOW RATED VCEO
Extended SOA @ 1 s, 10 s 1 s 10 s 1 ms
10 IC, COLLECTOR CURRENT (AMPS) 8 6 4 2 0 TC 100C GAIN 4 LC = 500 H VBE(off) -5 V 0V -2 V 100 200 300 400 500 600 700 800 VCEV, COLLECTOR-EMITTER CLAMP VOLTAGE (VOLTS)
10
20 30
50 70 100 200 300 500 1000
0
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 6. Maximum Forward Bias Safe Operating Area
Figure 7. Maximum Reverse Bias Switching Safe Operating Area
1 0.8 0.6 0.4 0.2 0 20 THERMAL DERATING SECOND BREAKDOWN DERATING
40
60
80
100
120
140
160
TC, CASE TEMPERATURE (C)
Figure 8. Forward Bias Power Derating
There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC -- VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 6 is based on TC = 25C; TJ(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC 25C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 6 may be found at any case temperature by using the appropriate curve on Figure 8. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 7) is discussed in the applications information section.
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
POWER DERATING FACTOR
1 0.7 0.5 0.2 0.1 0.07 0.05 0.02 D = 0.5 D = 0.2 D = 0.1 D = 0.05 D = 0.02 D = 0.01 0.02 t1 t2 SINGLE PULSE 0.05 0.1 0.2 0.5 1 2 t, TIME (msec) 5 DUTY CYCLE, D = t1/t2 10 20 P(pk) RJC(t) = r(t) RJC RJC = 1.56C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 50 100 200 500 10 k
0.01 0.01
Figure 9. Typical Thermal Response for MJE13007
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MJE13007
SPECIFICATION INFORMATION FOR SWITCHMODE APPLICATIONS
INTRODUCTION
The primary considerations when selecting a power transistor for SWITCHMODE applications are voltage and current ratings, switching speed, and energy handling capability. In this section, these specifications will be discussed and related to the circuit examples illustrated in Table 2.(1)
VOLTAGE REQUIREMENTS
Both blocking voltage and sustaining voltage are important in SWITCHMODE applications. Circuits B and C in Table 2 illustrate applications that require high blocking voltage capability. In both circuits the switching transistor is subjected to voltages substantially higher than VCC after the device is completely off (see load line diagrams at IC = Ileakage 0 in Table 2). The blocking capability at this point depends on the base to emitter conditions and the device junction temperature. Since the highest device capability occurs when the base to emitter junction is reverse biased (VCEV), this is the recommended and specified use condition. Maximum I CEV at rated VCEV is specified at a relatively low reverse bias (1.5 Volts) both
at 25C and 100C. Increasing the reverse bias will give some improvement in device blocking capability. The sustaining or active region voltage requirements in switching applications occur during turn-on and turn-off. If the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn-on and the pulsed forward bias SOA curves (Figure 6) are the proper design limits. For inductive loads, high voltage and current must be sustained simultaneously during turn-off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as a Reverse Bias Safe Operating Area (Figure 7) which represents voltage-current conditions that can be sustained during reverse biased turn-off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode.
(1) For detailed information on specific switching applications, see (1) ON Semiconductor Application Note AN719, AN873, AN875, AN951.
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Table 1. Test Conditions For Dynamic Performance
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
VCC 1 F 150 3W 100 3W MPF930 MPF930 +10 V 50 500 F Voff MUR105 MJE210 150 3W MTP12N10 1 F RB1 RB2 A IB IB TUT IC 5.1 k VCE 51 D 1 -4V MTP8P10 MTP8P10 100 F L MUR8100E Vclamp = 300 Vdc +125 V RC RB TUT SCOPE
RESISTIVE SWITCHING
+15 V
TEST CIRCUITS
COMMON
V(BR)CEO(sus)
Inductive Switching L = 200 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1
RBSOA L = 500 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1 VCC = 125 V RC = 25 D1 = 1N5820 OR EQUIV.
CIRCUIT VALUES
L = 10 mH RB2 = 8 VCC = 20 Volts IC(pk) = 100 mA
TEST WAVEFORMS
IC ICM t1 VCE VCEM TIME
tf CLAMPED tf UNCLAMPED t2 t
t1 ADJUSTED TO OBTAIN IC Lcoil (ICM) t1 VCC t2 Lcoil (ICM) Vclamp VCE IB1 IB
TYPICAL WAVEFORMS
VCE PEAK
25 s +11 V
tf
0 9V tr, tf < 10 ns DUTY CYCLE = 1.0% RB AND RC ADJUSTED FOR DESIRED IB AND IC
Vclamp t2 t
TEST EQUIPMENT SCOPE TEKTRONIX 475 OR EQUIVALENT
IB2
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MJE13007
VOLTAGE REQUIREMENTS (continued)
In the four application examples (Table 2) load lines are shown in relation to the pulsed forward and reverse biased SOA curves. In circuits A and D, inductive reactance is clamped by the diodes shown. In circuits B and C the voltage is clamped by the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. A snubber network or an additional clamp may be required to keep the turn-off load line within the Reverse Bias SOA curve. Load lines that fall within the pulsed forward biased SOA curve during turn-on and within the reverse bias SOA curve during turn-off are considered safe, with the following assumptions: 1. The device thermal limitations are not exceeded. 2. The turn-on time does not exceed 10 s (see standard pulsed forward SOA curves in Figure 6). 3. The base drive conditions are within the specified limits shown on the Reverse Bias SOA curve (Figure 7).
CURRENT REQUIREMENTS
An efficient switching transistor must operate at the required current level with good fall time, high energy handling capability and low saturation voltage. On this data sheet, these parameters have been specified at 5.0 amperes which represents typical design conditions for these devices. The current drive requirements are usually dictated by the VCE(sat) specification because the maximum saturation voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage.
SWITCHING REQUIREMENTS
SWITCHING TIME NOTES In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and any coil driver, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp trv = Voltage Rise Time, 10-90% Vclamp tfi = Current Fall Time, 90-10% IC tti = Current Tail, 10-2% IC tc = Crossover Time, 10% Vclamp to 10% IC An enlarged portion of the turn-off waveforms is shown in Figure 12 to aid in the visual identity of these terms. For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN222A: PSWT = 1/2 VCCIC(tc) f Typical inductive switching times are shown in Figure 13. In general, trv + tfi tc. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at 25C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a "SWITCHMODE" transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100C.
In many switching applications, a major portion of the transistor power dissipation occurs during the fall time (tfi). For this reason considerable effort is usually devoted to reducing the fall time. The recommended way to accomplish this is to reverse bias the base-emitter junction during turn-off. The reverse biased switching characteristics for inductive loads are shown in Figures 12 and 13 and resistive loads in Figures 10 and 11. Usually the inductive load components will be the dominant factor in SWITCHMODE applications and the inductive switching data will more closely represent the device performance in actual application. The inductive switching characteristics are derived from the same circuit used to specify the reverse biased SOA curves, (see Table 1) providing correlation between test procedures and actual use conditions.
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MJE13007
SWITCHING PERFORMANCE
10000 VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25C PW = 25 s 10000 7000 5000 tr 2000 1000 700 500 tf td 10 1 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) 7 8 9 10 200 100 1 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) 7 8 9 10 VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25C PW = 25 s
ts
t, TIME (ns)
100
Figure 10. Turn-On Time (Resistive Load)
t, TIME (ns)
1000
Figure 11. Turn-Off Time (Resistive Load)
IC 90% Vclamp tsv trv tc Vclamp IB 90% IB1 10% Vclamp 10% IC 90% IC tfi
10000 Vclamp tti t, TIME (ns) 5000 2000 1000 500 200 100 50 20 TIME 10 0.1
IC/IB = 5 IB(off) = IC/2 Vclamp = 300 V LC = 200 H VCC = 15 V TJ = 25C
tsv
2% IC
tc tfi
0.2
0.3
0.5 0.7
1
2
3
5
7
10
IC, COLLECTOR CURRENT (AMP)
Figure 12. Inductive Switching Measurements
Figure 13. Typical Inductive Switching Times
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MJE13007
Table 2. Applications Examples of Switching Circuits
CIRCUIT SERIES SWITCHING REGULATOR
COLLECTOR CURRENT 16 A TC = 100C 8A TURN-ON TURN-OFF 400 V 1 VCC COLLECTOR VOLTAGE See AN569 for Pulse Power Derating Procedure. TURN-ON (FORWARD BIAS) SOA ton 10 s DUTY CYCLE 10% VO N COLLECTOR CURRENT TC = 100C 8A PD = 3200 W 2 300 V TURN-OFF TURN-ON + VCC Notes:
1
LOAD LINE DIAGRAMS
TURN-ON (FORWARD BIAS) SOA ton 10 s DUTY CYCLE 10% PD = 3200 W 2 300 V TURN-OFF (REVERSE BIAS) SOA 1.5 V VBE(off) 9 V DUTY CYCLE 10%
TIME DIAGRAMS
IC ton toff TIME VCE VCC t
A
VCC VO
+ Notes:
1
700 V 1
TIME
t
FLYBACK INVERTER
16 A
IC toff
VCC
B
TURN-OFF (REVERSE BIAS) SOA 1.5 V VBE(off) 9 V DUTY CYCLE 10% VCE VCC + N (Vo)
ton LEAKAGE SPIKE
t
VCC + N (Vo) + LEAKAGE SPIKE 400 V 1 700 V 1 COLLECTOR VOLTAGE
VCC t
VCC + N (Vo)
See AN569 for Pulse Power Derating Procedure. TURN-ON (FORWARD BIAS) SOA ton 10 s DUTY CYCLE 10% PD = 3200 W 2 300 V TURN-OFF (REVERSE BIAS) SOA 1.5 V VBE(off) 9 V DUTY CYCLE 10% VCE 2 VCC VCC + TURN-OFF VCC 400 V 1 COLLECTOR VOLTAGE See AN569 for Pulse Power Derating Procedure. TURN-ON (FORWARD BIAS) SOA ton 10 s DUTY CYCLE 10% PD = 3200 W 2 300 V 8A TURN-OFF TURN-ON + VCC 400 V 1 700 V 1 TURN-OFF (REVERSE BIAS) SOA 1.5 V VBE(off) 9 V DUTY CYCLE 10% VCE VCC 2 VCC 700 V 1 t ton
PUSH-PULL INVERTER/CONVERTER
16 A TC = 100C
IC toff t
COLLECTOR CURRENT
C
VCC
VO
8A
TURN-ON
Notes:
1
SOLENOID DRIVER
16 A TC = 100C COLLECTOR CURRENT VCC
IC ton toff t
D
SOLENOID
COLLECTOR VOLTAGE Notes:
1
t
See AN569 for Pulse Power Derating Procedure.
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MJE13007
PACKAGE DIMENSIONS TO-220AB CASE 221A-09 ISSUE AA
SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04
-T- B
4
F T S
C
Q
123
A U K
H Z L V G D N R J
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Notes
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SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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